| 摘要 |
PURPOSE:To quickly exchange the various types of information data by transferring data on a ROM where a certain type of data is written in parallel to a RAM and then removing said ROM from an information equipment. CONSTITUTION:In a normal mode a CPU 3 sets the control signals, the inverse of CS0-CS5 of a RAM 1, a ROM 2 and a display driver at high levels and inactivates the IC other than that of the CPU 3 itself. A ROM part B is connected to an equipment main body A as shown in the diagram and then the CPU 3 gives the output of a low level, i.e., an address 0 to addresses A0-A11 with input of KEY1. In such case, the data bus of the CPU 3 is set at high impedance. Then the inverse of CS2, CS3 and CS5 are set at low levels together with the RAM 1 set under a stand-by state for writing and the ROM 2 is set to the address outputted from the CPU 3. Then the ROM 2 is removed from the main body A.
|
