| 摘要 |
A CMOS data register includes a master stage and a slave stage. The master stage is formed of first transfer gates and first storage devices. The slave stage is formed of second transfer gates, second storage devices and third transfer gates. The transfer gates and storage devices are formed of MOS transistors of one conductivity which decreases layout complexity and reduces the amount of chip area required. The data register is formed of a fewer number of transistor components, thereby reducing the loading on the clock signals. |
