| 摘要 |
The addition-subtraction unit according to the subject of the invention stores the carry at every addition, and processes it at the next addition. Similarly, at every subtraction the carry is stored and processed at the next subtraction. The subtractions are done additively, by processing the nine's complement of the subtrahend instead of the subtrahend. As its main circuit, this addition-subtraction unit has an adder circuit (1), which consists of 36 individual adder circuits (20) which only process the value 2. The value 1 is processed using a dual full adder (6) and a one upwards shift circuit (10). The value 5 is split into the partial summands 4 and 1. <IMAGE>
|
