| 摘要 |
PURPOSE:To prevent a transmission error due to the integration of wave form distortion from occurring by passing an input signal in a transparent state and removing the wave form distortion. CONSTITUTION:A clock signal generation part 11 which generates plural out-of- phase clock signals whose frequency is at least twice as high as that of an input signal, a delay signal generation part 12 which generates a signal having a certain time delayed behind the input signal, a phase detection part 13 which detects the best phase for latching the input signal with the delay signal, an up/down counter 14 where detected phase data is preset, and an up/down signal generator 16 which operates the counter according to the comparison result between the phase detected by the phase detection part every time the input signal rises after the presetting and the phase set in the counter, are provided. Then, a clock signal selection part 15 which selects one of the clock signal according to the contents of the high-order digits of the counter and a latch part 17 which latches the input signal with the selected clock signal, are provided.
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