| 摘要 |
PURPOSE:To exactly generate a timing signal even if the clock of a transmitting side is quicker than that of a receiving side, by providing a pair of write signal generating circuits on a data reception control circuit, operating them alternately and reducing the operating period of one piece of write signal generating circuit. CONSTITUTION:Whenever a data strobe signal is received, a switching circuit 51 outputs alternately the received data strobe signal from one of two pieces of output terminals thereof. Each write signal generating circuits 52, 52' generates a timing signal, whenever the data strobe signal is supplied from the switching circuit 51. In such case, each write signal generating circuit 52, 52' can generate exactly the timing signal, since the data strobe signal is supplied alternately, that is to say, since the operating period is reduced to half. The timing signals which are generated separately and alternately by each write signal generating circuit 52, 52' is brought to OR by an OR circuit 53, and outputted as one timing signal. |
