| 摘要 |
PURPOSE:To execute a time division multiplexing by supplying a master clock from a time division multiplexing encoder, to plural pieces of digital signal sources in which a sampling frequecy and the number of quantizing bits are the same. CONSTITUTION:In a time division multiplexing encoder 3, a multiplexing frame synchronizing pattern and a sample data words(music, an announce data, etc.) WA, WB and an error correcting code are added to a time division multiplexing format and outputs a multiplexing data signal MD. A transmission rate identifying means 5 identifies a VCO input voltage of a PLL circuit 5a by a voltage level identifying circuit 5b, generates a transmission rate identifying signal corresponding to a voltage level, and can supply its generated signal to a time division demultiplexing decoder 6. In such a way, a clock synchronization of the time division multiplexing encoder 3, and the sample data word of each digital signal source, which is inputted to the time division multiplexing encoder 3 can be executed, and the time division multiplexing can be executed.
|
