| 摘要 |
A power reset delay circuit is described which when energized provides a delayed output signal a predetermined time interval thereafter and which draws substantially zero current when turned off. The delay circuit comprises a first transistor which when turned on disables the discharge path to a capacitor while enabling the charging of the same through the base-emitter path of a second transistor the emitter of which is connected to the base of a third transistor. A P-type semiconductor ring is formed about the collector of the third transistor and in combination therewith functions as a comparator to provide the output signal when the third transistor saturates due to the charging of the capacitor reducing the voltage level at the base thereof.
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