SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PURPOSE:To allocate two control signals to a signal terminal by using an inhibiting circuit which inhibits in terms of circuit the malfunction cased by the timing shift of a chip selection signal. CONSTITUTION:An inhibiting circuit inhibits such a malfunction where the 1st control signal is allocated at a high or low level of a control terminal and the 2nd control signal is active in case the 1st control signal ends earlier than the chip selection signal after the 2nd control signal is made active at an inverse level of the 1st control signal. The signal B' produces an error if the timing shift is produced between the CS and A/B signals. This error, however, is rejected by securing an AND between the CS signal and the signal (b) obtained through a NOR between the A/(the inverse of B) signal and the signal (a) after the signal A/(the inverse of B) passed through a delay circuit 5. The time con stant of a delay circuit can be decided by the relation between the maximum value of either one of CS signals conceivable in a system and the pulse width of the control signal A/(the inverse of B). Thus two control signals can be allocated to a single terminal.