发明名称
摘要 PURPOSE:To obtain a pulse width modulation circuit without malfunction, by outputting an output pulse until a counter is again preset, through the counting of a counter is stopped, when the counter preset with a digital value counts a maximum counting value. CONSTITUTION:After digital modulation signals d1-dn are stored in a preset circuit 4, they are preset in a binary counter 1. A clock (a) is applied to the counter 1 via a gate 5 and the counter 1 counts this clock (a). When the content of the binary counter 1 reaches a maximum count value, a detector 6 detects it, a detected output is applied to an output generator 7 and a gate 5 to close the gate 5. At every period corresponding to a period when the counter 1 reaches the maximum value from zero, the counter 1 is preset from the preset circuit 4. An output pulse width corresponding to the digital modulation signals d1-dn can be obtained from the output circuit 7.
申请公布号 JPS6258572(B2) 申请公布日期 1987.12.07
申请号 JP19810073715 申请日期 1981.05.15
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMAGUCHI SEIJI;HASHIRANO MASARU;YABU TOSHIOMI;OOTA YUTAKA
分类号 H03M1/82 主分类号 H03M1/82
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