| 摘要 |
PURPOSE:To flexibly branch bits at a high speed by efficiently using a control memory even if only part of data is involved in branching when bits are branched in plural directions according to the contents of data. CONSTITUTION:It is assumed that the data 42 is generated by a bit selection and compression circuit 104 and put in a register 106. A branch address generator circuit 107, adding data in the register 106 to basic address in the NMA field 128 of a microinstruction, generates an address for a branch destination. The generated address enters a microaddress register 108 and a microinstruction at the branch destination is taken out. If two-bit information is reflected on the branch address like three branches 4-6, all the selected bits concentrate on a low order by passing them through a bit selection and comparison circuit 13. As a result, they are branched into continuous four words starting in a four-word boundary in any case. If basic addresses 0, 4 and 8 are given to the branches 4-6, bits can be efficiently allocated.
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