| 摘要 |
PURPOSE:To increase the data transfer speed by eliminating the confirmation of a ready flag when data are sent to an I/O device from a CPU. CONSTITUTION:When a CPU5 transfers data to an I/O device 6, the transfer data S1 is delivered to a data register 7 and a data transfer signal S2 is simultaneously outputted through a strobe terminal ST. The signal S2 is supplied to an AND gate 8. In such case no ready signal S3 is outputted from a data register 7 of the device 6 as long as the register 7 is not possible yet to fetch data. Thus the gate 8 is closed and no data transfer signal S4 is supplied to the acknowledge terminal ACK of the CPU5, therefore the CPU5 is kept waiting as it is. In such a way, it is not needed to conform a ready flag in a data transfer mode, therefore the data transfer speed is substantially increased. |
