| 摘要 |
PURPOSE:To prevent the influence due to fading, etc., by providing a free run request part to free-run a reproducing clock signal at a clock reproducing part and holding a clock signal regenerated once at the clock regenerating part. CONSTITUTION:Since a request signal is not outputted from a free run request circuit 7 when the reduction of a receiving signal is not reduced, a clock signal regeneration circuit (clock signal extracting circuit 3, PLL 4, split phase decoder circuit 5 and pattern matching circuit 6) executes a usual action. When the receiving signal is reduced, a regenerating clock signal is not outputted, the receiving signal becomes higher, and when the regenerating clock signal is outputted again, the output of the circuit 6 is outputted to the circuit 7. By the output signal, a free run request signal is outputted from the circuit 7, and inputted to a free run gate 44. By inputting the free run request signal, the free run gate 44 prevents the correcting request signal from being inputted to a variable phase frequency dividing circuit 42. For this reason, a PLL circuit 4 is fixed to the frequency of the regenerating clock signal. At this time, the phase of the free-run regenerating clock signal is also simultaneously fixed. |
