| 摘要 |
A digital signal processing circuit comprises a multiplier section (17) for multiplying signals each of a plurality of bits by each other to produce a product signal in which more significant bits are given a larger unit delay, the amount of delay increasing at intervals of a number of bits, and an adder section (22) for adding the product signal from the multiplier section (17) to another summand signal of a plurality of bits, the multiplier section (17) and the adder section (22) being formed in the same semiconductor chip. |
