| 摘要 |
<p>PURPOSE:To prevent the reading errors of information due to leakage occurring between adjacent memory cells by setting a 3rd decoder between a memory cell matrix and a power supply part. CONSTITUTION:An end of each data line is connected to a column address decoder YDCR1 and the other end of the data line is connected to another column address decoder YDCR2 (the 3rd decoder). The YDCR2 is set between a memory cell array M-ARY and a precharging MISFET which supplies the precharging potential Vcc to the M-ARY. A precharging circuit consists of an n channel MISFET which receives a precharging signal phiPC through its gate. A MISFETQdc conducts by the opposite-phase precharging signal phiPC and therefore a common data line CD, etc. are set at an earth potential. Thus the data lines except for the selected ones can always be released and the reading errors of the information stored in a memory cell can be avoided.</p> |
