发明名称 LOGICAL INTEGRATED CIRCUIT
摘要 PURPOSE:To reduce the time until an output level is confirmed after a FF for input extraction fetches an input signal by combining plural FFs with different threshold value and a majority decision circuit. CONSTITUTION:A majority decision circuit 10 uses an inverter 8 in the circuit 10 to invert an level signal (an output level of at least >= 2 FFs in FFs 1-3 made identical to each other) and the result is outputted externally from an output terminal 11. The majority decision circuit 10 is acted to output an H level signal forcibly from the output terminal 11 when the FF 3 is brought into the metastable state and the FFs 1, 2 are brought into H aud L level respectively. Thus, the time until the output level is confirmed after the input fetch FF fetches an input signal is decreased.
申请公布号 JPS62276924(A) 申请公布日期 1987.12.01
申请号 JP19860119211 申请日期 1986.05.26
申请人 HITACHI LTD 发明人 NAKAMURA YOSHIHIDE
分类号 H03K19/0175;H03K19/00;H03K19/01 主分类号 H03K19/0175
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