| 摘要 |
PURPOSE:To reduce the memory capacity assigned to a high speed information channel by providing hierarchically a holding memory controlling the write address of a call memory and a holding memory controlling a read address. CONSTITUTION:The data from an input highway 31 is written in a call memory 30 and the read data is outputted to an output highway 32. The write address of the memory 30 is indicated by the read data of a hierarchical holding memory 34 and the read address of the memory 30 is indicated by the read data of a hierarchical holding memory 35. Then to a time switch 1 the memory 30 and the memory 34 and 35 are respectively by one address corresponding to an information channel and the time switch raises an access frequency to the memory to process corresponding to a high speed information channel. Therefore the more the speed ratio between the high speed channel and the low speed channel becomes, the less the hardware amount becomes.
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