| 摘要 |
PURPOSE:To improve the linearity of the output of a signal meter and to output continuously a multi-path quantity by synthesizing outputs of all amplifiers in individual stages of an intermediate frequency amplifying circuit consisting of >=4 stages of amplifiers and outputting the synthesized result as a signal strength display signal. CONSTITUTION:The intermediate frequency amplifyings circuit consists of amplifiers 3-7, and outputs of these amplifiers pass capacitors 8, 19, 9, 20, and 10, rectifying circuits 11, 21, 12, 22, and 13, and amplifiers 14, 23, 15, 24, and 16 and are synthesized in an adder 17 by addition, and the result is outputted to a signal meter output terminal 18. consequently, a voltage proportional to the voltage inputted to an intermediate frequency input terminal 1 is displayed on the signal meter. |
