| 摘要 |
PURPOSE:To efficiently process a vector instruction with a mask by controlling an operation so as not to execute unnecessary reading of an operand corresponding to a mask suppressing bit. CONSTITUTION:Address calculating information in an instruction word read out from a storage controller 21 is set up in an instruction register 101. An index and a base value are read out from a general register 103 based on the address calculating information. An address formed by an address adder 110 is set up in a vector address register 106. The mask word set up in a vector mask register 111 is inputted to a continuous mask bit number counting circuit 113 through a justification circuit 112. The output of the circuit 113 is applied to a vector mask control circuit 114. The address adder 110 adds an address increment value to a vector address to find out an operand address.
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