发明名称 |
Method and apparatus for validating prefetched instruction |
摘要 |
A method and data processing system for validating prefetch instruction. The system includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit. The system further includes a circuit for prefetching instruction words to be executed subsequently to a presently executing instruction and a circuit for verifying the validity of the prefetched instruction word prior to execution thereof by the execution unit, and a circuit for causing the instruction unit to a fault condition only when the execution of an invalid instruction is begun.
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申请公布号 |
US4710866(A) |
申请公布日期 |
1987.12.01 |
申请号 |
US19860930941 |
申请日期 |
1986.10.07 |
申请人 |
MOTOROLA, INC. |
发明人 |
ZOLNOWSKY, JOHN;CRUDELE, LESTER M.;SPAK, MICHAEL E. |
分类号 |
G06F9/38;(IPC1-7):G06F11/00 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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