发明名称 |
Partitioned scan-testing system |
摘要 |
A test partitionable logic circuit comprises a plurality of functional modules (26a)-(26n). Each of the functional modules is interfaced with the exterior of the logic circuit with a data bus (20), address bus (16) and a control bus (12). Each of the modules (26) is addressable through an address decode/select circuit (52) to operationally isolate the select modules and define a test boundary. Test data is scanned into a serial chain of shift register latches (SRL's) which are connected in a daisy chain configuration. The defined test boundary allows each of the modules to be separately selected and tested such that the test program for an individual module is separate and distinct.
|
申请公布号 |
US4710931(A) |
申请公布日期 |
1987.12.01 |
申请号 |
US19850790543 |
申请日期 |
1985.10.23 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
BELLAY, JEFFREY D.;POWELL, THEO J. |
分类号 |
G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/3185 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|