| 摘要 |
PURPOSE:To output read data at optional timing by using two control signals supplied from outside to control the transmission of the read data given to the 2nd latch circuit from the 1st latch circuit and the timing outputting to an external terminal from the 2nd latch circuit. CONSTITUTION:An output signal of a sense amplifier circuit SA is fetched by the 1st latch circuit DL 1 in response to a timing signal phis1. While an output signal of the circuit DL1 is fetched by the 2nd latch circuit DL2 in response to a timing signal phis2. Then a timing signal phisd is produced when both signals phis1 and phis2 are set at high levels at the same time. Thus the output signal of the circuit SA is transmitted directly to the circuit DL2 with no intervention of the circuit DL1. Furthermore, an output signal of the circuit DL2 is transmitted to output MOSFETs Q9 and Q10 by a timing signal phioe and then outputted to an external primary device, etc.
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