| 摘要 |
The central processing unit of a data processing system employs a decoder 40 to decode macroinstructions held in an instruction register 19 under the control of a program counter 20. Each decoded macroinstruction provides a sequence of first microinstructions on an 18-bit bus 39. Each first microinstruction comprises a 4-bit address field applied to a sequencer 33 which also receives bits from the decoder 40 and addresses a ROM 31 which provides the first microinstructions. A 6-bit field of each first microinstruction addresses another ROM 32 which provides one of 64 second microinstructions of 33 bits each, HORM O-32. Fields of the second microinstructions are modified in accordance with two 4-bit modifier fields V1 and V2 from the first microinstruction in a modification circuit 34 which provides 35-bit output microinstructions HCOMT 0-34. These output microinstructions are applied to a decoder 35 whose outputs control the machine states of the CPU. A system bustiming system and a frequency synthesizer are also provided. |
