| 摘要 |
PURPOSE:To surely write data in a buffer RAM and to contrive the convolution processing to high speed by providing a delay circuit like a pipeline register behind an adder and matching the intermediate operation result from the adder to the timing of write to the buffer RAM. CONSTITUTION:The output from an adder 5 is applied to the delay circuit, for example, a pipeline register 7. The pipeline register 7 consists of, for example, a D flip flop and delays the output from the adder 5 up to the start time of the next convolution processing cycle. The output of the pipeline register 7 is applied to a bus buffer 8, and the bus buffer 8 is controlled to turn on and off by the control signal from a controller 2, and the write to a buffer RAM 9 from the pipeline register 7 is permitted when the bus buffer 8 is turned on. Since the output of the adder 5 is delayed by the pipeline register 7, the write start address to the buffer RAM 9 is shifted by +1 at every time of addition of the intermediate operation result. |
