| 摘要 |
PURPOSE:To detect a timing to perform a skew correction by a simple circuit by outputting a skew correction signal synchronously with a head change over signal and a reproducing horizontal synchronizing signal. CONSTITUTION:An envelope comparison signal S1 is latched to a D-FF5 by the rise edge of the reproducing horizontal synchronizing signal (HSYNC) synchronized by a clock constituted of a clock CK and three D-FFs 1-3 and a NOR gate 4 and applied to a head amplifier as the head change over signal S2. The head changeover signal S2 triggers a write prohibiting signal (WE) generating D-FF9 by a rise edge signal S3 according to D-FFs 6, 7 and an EX-NOR gate 8 to bring the WE signal to 'H' level and the writing to a line memory is prohibited. Accordingly, the WE signal indicates the timing of generating the skew and when the read/write of the memory is controlled by this signal, the skew can be eliminated.
|
