| 摘要 |
PURPOSE:To accelerate the operation of the title MOS integrated circuit by a method wherein the first type logic circuit comprising the N channel loading MOSFETs and P channel driving MOSFETs and the second type logic circuit comprising the P channel loading MOSFETs and N channel driving MOSFETs are provided. CONSTITUTION:The title MOS integrated circuit is composed of the first region 6 containing multiple numbers of the first type logic circuits comprising N channel loading MOSFETs 18, 21 and P channel driving MOSFETs 16, 17, 10, 20 as well as the second region 5 containing multiple numbers of the second type logic circuits comprising P channel loading MOSFETs 11, 14 and N channel driving MOSFETs 12, 13, 15 formed on a semiconductor substrate. In such a constitution, three types of logic circuits, i.e., an NOR circuir, an NAND circuit and an inverter can be used so that both the number of logic gate circuits and the step number of the maximum logic gate circuits from input to output may be decreased to form the MOS integrated circuit to be operated at high speed. |
