| 摘要 |
PURPOSE:To prevent the generation of an interfacial deterioration and to contrive reduction in the gate capacitance of the title transistor by a method wherein a gate electrode is provided on the gate region formed by ion-implanting impurities through a window provided on a mask layer, the mask layer is removed, and after the surface of a substrate has been removed, a source region and a drain region are formed. CONSTITUTION:As the surface of the GaAs substrate 7, the interfacial characteristics of which are deteriorated by the application of heat, is removed after a P<+> region 2 has been formed, the problem of deterioration in element characteristics resulting from the interfacial characteristics between the GaAs and an SI3N4 film, generated on the J-FET which was heretofore in use, is not generated. In the FET which was heretofore in use, the width of a diffused P<+> region in the state as it is became the gate length of the completed FET, but the circumferential part of the P<+> region 2 in the GaAs substrate is removed by etching, and the gate length can be made short easily. Therefore, the effective gate length of the substrate can be made to 1.0 mum or less. Besides, as the circumferential part of the P<+> region 2 is removed, no P-N junction is present on the side wall, and a gate capacitance can be reduced to that extent.
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