| 摘要 |
PURPOSE:To speed up arithmetic processing including size conversion by generating an overflow signal by AND operation between the detection signal of a detecting circuit and the overflow output of an arithmetic operation unit. CONSTITUTION:The overflow signal OVF is generated by detecting one of bits corresponding to digits higher than the most significant digit bit of an output register R4 for data size conversion which consists of a smaller number of bits than the absolute value display data of the output signal of the arithmetic logical operation unit ALU being logic 1 when the absolute value display data is processed or by detecting the dissidence of even one of all of the bits corresponding to digits higher than the most significant digit bit on an output register R3 and the most significant digit bit of the register R3 when complementary number display data of '2' is processed. Thus, the overflow signal is generate directly and the arithmetic processing including the size conversion is speeded up. |
