发明名称 JITTER GENERATING CIRCUIT
摘要 PURPOSE:To impress jitter with a high precision without adjusting in a simple circuit constitution by using a random data string as a control signal to select a pulse signal from an input pulse train at random and outputting the selected pulse signal after delay of a certain time. CONSTITUTION:A clock is inputted to a clock terminal 6, and the pulse signal is inputted to an input terminal 1 syncbronously with the clock. A direct link 2 directly supplies the pulse signal to a changeover switch 4, and a delay circuit 3 supplies the pulse signal to the changeover switch 4 after delaying it by a certain time. A frequency dividing circuit 7 converts the speed of the clock inputted to the clock terminal 6 to 1/m-fold speed ((m) is a positive integer). A control data generating circuit 8 is operated by this 1/m-fold clock to generate random control data. The changeover switch 4 selects the direct link 2 or the delay circuit 3 in accordance with this control data to connect it to an output terminal 5. By this constitution, jitter is generated which is delayed by a certain time at random for every m-number of pulse signals.
申请公布号 JPS62274915(A) 申请公布日期 1987.11.28
申请号 JP19860118788 申请日期 1986.05.23
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 OBARA HITOSHI
分类号 H03K3/84 主分类号 H03K3/84
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