Shift register device for performing a synchronous division of the frequency of a binary clock and multiplexer using such a device

摘要

The invention relates to a shift register device for performing a synchronous division of a binary clock by an integer N, in which N - 1 successive "preset" parallel inputs of this register are connected to a level such that, applied to a selection input, it causes a shift in the chosen direction. The serial data input corresponding to this direction is connected to the binary level ensuring an initialisation when this level is applied to a selection input. Likewise for the "preset" input immediately ahead of the N - 1 preceding parallel inputs on the serial data input side. The output corresponding to the N - 1<st> input is looped back to a selection input. This device sets itself going. Application in particular in a multiplexer. <IMAGE>