| 摘要 |
This phase and frequency detector, receiving two logic input signals R and V, comprises a set of 2k+2 memory cells, cascade arranged and linked in twos by 2K+1 control cells, capable especially of transferring the information contained in the changes of state of the signals R and V, from the end memory cells to which they are respectively applied, and by each of the directions respectively, to a memory cell MUn or MDn (depending on whether the signal R is ahead or delayed with respect to the signal V), this cell then giving square waves the duty factor of which is proportionate to the instantaneous phase shift DELTA phi between the signals R and V, when (2 pi -1)n<¦ DELTA phi ¦< pi . |
