| 摘要 |
In a frequency synthesizer with phase-locked loop in which the output signal from a voltage controlled oscillator is frequency-divided by a variable frequency dividing circuit and the frequency-divided one, together with a reference frequency signal, is applied to a phase comparator and the output signal from the phase comparator is fed back to the voltage control oscillator, the variable frequency dividing circuit is comprised of a first variable frequency divider for frequency-dividing the frequency of the output signal from the voltage controlled oscillator into a 1/K frequency, a second variable frequency divider for frequency-dividing the frequency of the output signal from the first variable frequency divider into a 1/m frequency, and a rate multiplier which receives the output signal from the second variable frequency divider to produce Q pulses (Q is an integer between 0 to P-1 where P is an integer) when receiving P input pulses, and to change the frequency dividing ratio K of the first variable frequency divider. |
