| 摘要 |
PURPOSE:To prevent the increase in the memory capacity and to attain stable operation by arranging the plural number of ROMs, and shifting the phase of a signal supplying an address of the ROMs. CONSTITUTION:An NRZ signal inputted to a data input port 1 is inputted to an N-bit shift register 2, where the signal is shifted by one by bit at T sec each and stored therein. The content of storage of the shift register 2 is fed to ROMs #151, #252 to form part of addresses of ROMs 51, 52. A signal of M3=M2-1-bit except the LSB-bit among M2-bit of an output signal of a binary counter 4 is supplied as a part of the address of the ROM #151. Simultaneously, all the said M3 bits are fed to a phase shifter 8, where the signal (M3-bit) whose phase is retarded by phi si given to the ROM #252 to part of the address. Thus, the operating speed of the ROMs 51, 52 is halved and the capacity of the ROMs is halved.
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