| 摘要 |
PURPOSE:To obtain a memory cell for performing a DRAM of approx. 64Mbit by using a trench type capacitor buried through a thin insulating film in a P<+> type substrate, and an N-channel MIS transistor of vertical SOI structure having an upper part as a source electrode. CONSTITUTION:A trench type capacitor of N<+> type polysilicon 24 buried through a thin insulating film 25 in a P<+> type substrate 21, and an N-channel MIS transistor of vertical SOI structure having the upper part of the polysilicon 24 as a source electrode are employed. For example, a trench structure is formed by RIE on the substrate 21, and the polysilicon 34, a P<-> type polysilicon 23 and an N<+> type polysilicon 22 are formed through the film 25. Further, after a field oxide film 28 and a gate oxide film 26 are formed, a gate electrode 27, a word line 29 and an interlayer insulating film 30 are formed, a contact hole is then opened to form a bit line 31, thereby obtaining a 1-transistor type memory cell in which a vertical MOS transistor is laminated on the trench type data storage capacitor. |
