| 摘要 |
PURPOSE:To evade malfunction by inhibiting different values of input signals from being sent to circuits of the post-stage to block noise or the like if the values of input signals are not the same consecutively two times or over. CONSTITUTION:When outputs of D flip-flops 1, 2 are not coincident, an output Qc of an exclusive NOR gate 3 goes to '0', resulting that outputs of NAND gates 5, 6 are at logical '1' without fail, then an output Vin' of a flip-flop 7 is unchanged. When the outputs of the D flip-flops 1, 2 are coincident, the output Qc of the exclusive NOR gate 3 goes to '1', the inverse of an S input or the inverse of an R input of the flip-flop 7 goes to '0' by the logical '1' or '0' level of the output Q2 of the D flip-flop 2 and the output Vin' is changed or keeps the preceding state. Thus, so long as a signal having a time width including two leading edges or over of the clock phi is not inputted, the state of the flip-flop 7 is unchanged.
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