| 摘要 |
PURPOSE:To improve the digital signal processing capability by providing a register storing a sign code and a register storing a sign after addition correction between a digital signal processing processor and a code compression converting circuit. CONSTITUTION:A digital signal processing processor 1a outputs a sign in a linear code to a register 8 as it is. Then the processor 1a applies absolute processing to the linear code, adds a prescribed value and the result is outputted to a register 9. The sign code and the code subjected to addition and correction set to the registers 8, 9 are converted into a nonlinear PCM code by the code compression conversion circuit 4 and outputted with further inversion. Through the system above, since the number of program step number in the processor 1a is effectively reduce with a constitution minimizing the increase in the hardware, the digital signal processing capability is improved.
|
