| 摘要 |
PURPOSE:To reduce the number of signal lines by providing a PLL circuit capable of locking by the phase information of a synchronzing system of a video signal and extracting the clock signal synchronously with the phase information. CONSTITUTION:The signal of a frequency 4fsc is generated from a VCO 5 and frequency-divided into the signal of 2fsc by a 1/2 frequency divider 6. The frequency division signal is fed to other input of a phase detecor 3 and compared with a, e.g., 1-bit color burst signal fed from an input terminal 2. The phase comparison of the both is applied by the phase detector 3 and its error signal is converted into a DC by an LPF 4 and the oscillation frequency of the VCO 5 is controlled by the error of the DC voltage. As a result, a clock signal is obtained at an output terminal 7. Since it is not required to send the clock signal from the sending side to the receiving side together with a data, a signal line required for the transmission of the clock signal is eliminated. |
