| 摘要 |
PURPOSE:To maintain the normal operations set within a system and to improve reliability of a clock checking circuit by providing a circuit working in response to a clock into each circuit unit of a system terminal and comparing the outputs of these circuits with each other via a common comparator to check the clock. CONSTITUTION:When the working of this clock checking circuit is started, the signals SL and clocks CL are supplied to J-KFF circuits 51 and 52 respectively. Both circuits 51 and 52 produce signals Q1 and Q2 in terms of time series according to the input of the clock CL and under the condition that the logic '1' exists as the signal SL. These signals Q1 and Q2 are equal to each other in a normal operation mode and therefore a comparator 6 produces no error signal SE. In case the clock signal CL supplied to a unit circuit 3 or 3' set at the terminal of a clock distributing circuit is omitted or a false CL is produced due to the external or internal disturbance to cause input of extra clocks CL, both signals Q1 and Q2 are different from each other and therefore the comparator 6 produces the signal SE. THus an error processing sequence is started.
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