发明名称 CLOCK GENERATOR FOR DEMODULATION OF HIGH FREQUENCY COUNTER SYSTEM
摘要 PURPOSE:To easily generate a clock for demodulation corresponding to a bit rate by executing the counting in accordance with the number of counting changed in accordance with the bit rate change and executing the output to a clock circuit for demodulation by a counter circuit. CONSTITUTION:A counter circuit 9 executes the counting according to a control signal corresponding to the change of the bit rate of reproducing data outputted by a control circuit and the number of counting to receive the high frequency clock of a higher frequency compared with the bit rate and execute the changing corresponding to the control signal. The output signal of the circuit 9 is outputted to a clock circuit for demodulation and from the clock circuit, the clock for the demodulation corresponding to the bit rate of the reproducing data is outputted. Thus, the clock for the demodulation, which is stable to a temperature and an electric power source voltage and corresponds to the bit rate of reproducing data while the clock is of a simple circuit constitution, can be easily generated.
申请公布号 JPS62270070(A) 申请公布日期 1987.11.24
申请号 JP19860116361 申请日期 1986.05.19
申请人 MITSUBISHI ELECTRIC CORP 发明人 KONDO YASUO
分类号 H03K5/00;G11B20/14 主分类号 H03K5/00
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