| 摘要 |
PURPOSE:To detect a phase shift from the optimum timing of a recovered clock signal by detecting the timing where a clock pattern crosses a prescribed reference level and integrating output data. CONSTITUTION:A clock pattern for phase correction having a prescribed period is prepared as a part of input signals fed to an input terminal 20. A zero cross timing detection signal (d) outputted from a synchronization detecting circuit 27 is fed to a phase error detection circuit 28, where it is converted into a voltage signal by a D/A converter circuit 29 and the signal is fed to a voltage- controlled variable phase shifter 25. Thus, the feedback loop is formed during the clock pattern period so as to form the discrimination result of the circuit 28 to be 0 and phase control is applied so that an inverted clock signal 9b is fed to an A/D conversion circuit 22 the timing optimum to the data detection. |
