Arrangement for generating a clock signal

摘要

A clock signal is derived from a biphase-modulated signal, by means of a controllable clock signal source. The polarity of the received signal is sampled at two sampling instants having a fixed relationship. The polarity samples are added modulo-2 and the resultant signal controls the controllable clock signal source. A false-synchronization detector includes inter alia a modulo-2 adder for comparing polarity samples in consecutive symbol intervals and a counter for counting consecutively equal polarity samples.