发明名称 |
Integrated circuit having latch circuit with multiplexer selection function |
摘要 |
An integrated circuit having a latch circuit with a selection function includes a selection circuit having a plurality of logic circuits each capable of presenting three output states depending on a selection signal supplied thereto, a latch circuit having a bistable circuit composed of first and second logic inverting circuits, and a connection system for supplying an output of the selection circuit to an input of the latch circuit. An output resistance of the second logic inverting circuit is set to be at least ten times as high as an output resistance of any one of the logic circuits which make up the selection circuit.
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申请公布号 |
US4709173(A) |
申请公布日期 |
1987.11.24 |
申请号 |
US19860864466 |
申请日期 |
1986.05.19 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
NISHIMICHI, YOSHITO;UYA, MASARU;KANEKO, KATSUYUKI |
分类号 |
H03K3/037;H03K3/012;H03K3/356;H03K17/00;(IPC1-7):H03K3/356;H03K19/094 |
主分类号 |
H03K3/037 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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