| 摘要 |
PURPOSE:To extract a synchronizing signal acurately even for an input signal whose change point phase is divided into two due to jitter by applying addition/ accumulation while regarding a count of a frequency division circuit in detecting a change point as a coded binary number and changing the frequency division if the accumulated value exceeds a positive or negattive prescribed value. CONSTITUTION:An input signal B1 whose change point is bipolar due to jitter is inputted to an input terminal 6. When the change point signal B2 appears in the timing t1, '-2' is fed to a register 3, and when the change point signal B2 appears the timing of t2, '+2', is fed thereto. If the phase of the count B4 is deviated forward by one clock, the accumulated value in the register 3 exceeds a positive prescribed value, e.g., +64 finally, a frequency divider 5 acts as a 1/17 frequency divider only once and the phase of the count B4 is retarded by one clock. If the phase of the count B4 is retarded, the register content is lower than a negative prescribed value, e.g., -63, the frequency divider 15 acts as a 1/15 frequency divider once similarly to correct the phase of the count B4. |
