| 摘要 |
PURPOSE:To exactly secure a fact that plural input/output controllers complete the reception of an interruption, respectively, by providing a common register which can execute read/write from each input/output controller on an input/ output device, and checking the state of the reception by other input/output controller. CONSTITUTION:For instance, when such an input/output interruption as a cartridge is set to a cartridge throw-in port, etc., is generated, an input/output interruption is informed to each interruption processing circuit 4-0-4-3 from an input/output interruption generating circuit 3. In such case, logic '1' is set onto bit #0 - bit #3 in a common register 5. Each interruption processing circuit 4-0-4-3 receiving the report of the input/output interruption reads the contents of the common register 5 successively and separately by a processing in accordance with a priority order, thereafter, receives the interruption concerned, if the bit corresponding to itself is logic '1'. Subsequently, the bit corresponding to itself in the contents of the common register 5 is changed to logic '1' and written in the common register 5, and the interruption is informed to the upper host. |
