| 摘要 |
PURPOSE:To attain excellent synchronizing pull-in characteristic and response characteristic by driving a hold circuit to a specific error region in case of asynchronizing state and to all error regions in case of synchronizing state. CONSTITUTION:The title circuit is provided with a circuit varying the integration time constant of a digital integration device depending on the quantity of an identification signal being an output of an A/D converter 26(1), the quantity of an error signal and the quantity of an identification signal being an output of an A/D converter 26(2), the output of the hold circuit 38 is driven only at a point of time corresonding to error information of a maximum level error region among outputs of a maximum level error decision circuit 36 in case of the asynchronizing state, the preceding state is held in case of other error regions and the hold circuit 38 is driven as to all the error regions in case of the synchronizing state by controlling the circuit above. Thus, the number of stages of reversible counters is varied based on the identification information and error information, and when the quantity of error is large, the integration time is reduced to quicken the response speed.
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