发明名称 VARIABLE DELAY CIRCUIT
摘要 PURPOSE:To improve the dependancy of delay with respect to an input frequency for a delay element by detecting a current conducted to a C-MOS inverter delay element, adding it to a delay control signal and cancelling the internal resistor of the C-MOS inverter by a negative output impedance at the driver side. CONSTITUTION:An IC being multi-stage connection of C-MOS inverters 2 is used as a delay element 1 and a delay time control signal S is given to the power terminal VDD of the delay element 1 as a control voltage through a drive circuit 4 from an adder 3. A current supplying circuit 5 (resistor) is connected in series with the power terminal and the detection signal is fed to an input delay time control signal at the adder circuit 3. The current of the deley element 1 is detected and fed back (added) to the driver side in such way to bring the drive source into a negative output impedance, thereby cancelling the internal resistor (r) of the C-MOS inverter 2, then even when the operating current changes by the input frequency, the frequency dependance such that the power voltage of the element is varied and the delay quantity is changed is reduced.
申请公布号 JPS62269411(A) 申请公布日期 1987.11.21
申请号 JP19860112050 申请日期 1986.05.16
申请人 SONY CORP 发明人 NAGASHIMA MASAO
分类号 H03K5/13;H03K5/133 主分类号 H03K5/13
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