| 摘要 |
PURPOSE:To improve the processing capacity of a DMA transfer control circuit by starting continuously the DMA transfer just with a single start applied from a processor and with no subsequent intervention of the processor. CONSTITUTION:A DMA transfer control circuit 12 contains an FIFO which stores the head addresses of plural areas of a main memory MM8 and the number of transfer words of each head address, a control circuit which gives a writing action to the FIFO via a processor 7, a control circuit which reads the transfer addresses and the number of transfer words out of the FIFO and loads them into a transfer address counter and a transfer word number counter, and a control circuit which accepts the DMA start and produces the bus release request timing. Then the circuit 12 performs the control to finish the DMA transfer for the first time after the FIFO is empty by the FIFO monitor control. No interruption is produced to a processor before the transfer is through with all set transfer blocks although the processor is set before start of the DMA transfer. Thus the software control is simplified and the processing capacity is never deteriorated with a DMA transfer control circuit. |
