| 摘要 |
PURPOSE:To reduce a required arithmetic time by providing a gate circuit and a multiplier receiving an exponent being an output from the 1st conversion table and an optional integer and multiplying the both and switching an output from the 1st conversion table and an output from the multiplier selectively and supplying the result to an adder/subtractor. CONSTITUTION:An element alpha<i> of a Galois field GF(2<m>) is converted into an exponent (i) by a conversion table 1 and inputted to a multiplier 7 together with the integer (l). The multiplier 7 applies the operation of iXl. The operation is applied by using 2<m>-1 as the system. In opening a gate 5 and closing a gate 6, an adder/subtractor 3 adds the result of multiplication iXl by the multiplier 7 with the exponent (j) being an output of a conversion table 2 and the result is iXl+j. Further, the obtained result iXl+j is subject to anti-logarithm conversion by an inverse conversion table 4 and the result is outputted as alphaiXl+j. Thus, the operation of alpha<j>X(alpha<i>)<l> is executed. Thus, as the error correction capability is increased, the reduction rate of the required arithmetic time is increased.
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