发明名称 EVALUATING CIRCUIT FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To simultaneously execute each test of an integrated circuit by loading a monitor circuit which has constituted a ring oscillator by providing a pseudo adder by odd stages on a full adder of necessary states, on the integrated circuit, and evaluating a DC/AC characteristic. CONSTITUTION:A pseudo adder PFA 12 of one stage is inserted into full adders FA11-13 of three stages, by which a ring oscillating circuit which is loaded on an integrated circuit is constituted. When control signals (B, C) are (0, 1), a ring oscillating circuit whose phase is shifted by 180 deg. by one round is constituted. When fan-out of each stage is '1', an equivalent circuit of 4 gates is constituted. Accordingly, when a delay time of the circuit is divided by 4, a delay time of 1 gate is derived. When the control signals (B, C) are (1, 0), an equivalent circuit of fan-out 2 and '1' is formed. By passing through 2 gates in each stage, in the same way, when the delay time is divided by 4, a delay time at the time of passing through both one gate of fan-out 2 and one gate of fan-out '1' is calculated.
申请公布号 JPS62267675(A) 申请公布日期 1987.11.20
申请号 JP19860112264 申请日期 1986.05.16
申请人 FUJITSU LTD 发明人 OSHIMA TOSHIO
分类号 G01R31/26;G01R31/28 主分类号 G01R31/26
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