发明名称 |
TEST SYSTEM FOR LOGICAL DEVICE USING HARDWARE LOGICAL SIMULATOR |
摘要 |
PURPOSE:To shorten the executing time of a test program with a hardware logical simulator by using a test program generating means set to an existing logical device to produce the test program. CONSTITUTION:A processing part 31 stores a test program into a memory part 32 from an external memory device 2 and simulates it. An initializing device 4 initializes the part 31 by the initial value of a register contained in the test program as well as the data area used by a test instruction train by the initial value of the data area contained in the test program. A comparing device 5 compares the result value of the test program executed via a hardware logical simulator 3 with that of the test program executed via a logical device 1 contained in the test program and judges the normal properties of the simulated device 1. |
申请公布号 |
JPS62267838(A) |
申请公布日期 |
1987.11.20 |
申请号 |
JP19860111394 |
申请日期 |
1986.05.15 |
申请人 |
NEC CORP |
发明人 |
SHIGETA TADASHI |
分类号 |
G06F11/22;G06F11/25;G06F11/26;G06F17/50 |
主分类号 |
G06F11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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