| 摘要 |
In a system where a plurality of memory boards, which can be of different sizes, are connected to a common address buss and data buss, it is disclosed that a binary adder adds the 2's complement of the contents of base address register with significant bits obtained from the address buss. A series of logic gates are connected to the output of the binary adder and a board size mask register. The logic gates perform a logical AND operation on the binary adder output and the output of board size mask register. The outputs from the logic gates in turn are connected to a multiple input NOR gate. When all the inputs are logical "zero", a board enable command is generated which will activate a memory board transceiver, which will then enable the specified memory board to receive or transmit data over the data buss. |
